Technical Field
The present disclosure relates to a semiconductor device including a wire bonding and a sintered region.
Description of the Related Art
As is known, today available are numerous electronic power devices, such as for example the so-called “power metal-oxide-semiconductor field-effect transistors” (power MOSFETs), or else “insulated-gate bipolar transistors” (IGBTs).
In the field of electronic power devices, there is particularly felt the need to provide packages that are able to guarantee not only supply of high currents, but also a high reliability.
In general, as shown in FIG. 1, an electronic power device 1 comprises a die 2, which is formed by a semiconductor body 4 and by a front metallization region 6, which extends over the semiconductor body 4. The semiconductor body 4 is made, for example, of silicon or silicon carbide and is arranged above a supporting element 8, to which it is fixed by interposition of a layer 10 known as “die-bonding layer 10”.
The electronic power device 1 further comprises a package 14, which in turn comprises, amongst other things, at least one wire 16 of conductive material, which contacts the front metallization region 6 for forming a corresponding wire bonding. The front metallization region 6 and the wire 16 thus form a so-called “chip-to-wire interface”.
The reliability of the above chip-to-wire interface is particularly critical and basically depends upon the materials of which the front metallization region 6 and the wire 16 are made.
In greater detail, as described in “Wire Bond Reliability for Power Electronic Modules—Effect of Bonding Temperature”, by Wei-Sun Loh et al., 8th International Conference on Thermal, Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro-Systems, EuroSimE 2007, devices are known in which the front metallization 6 is made of aluminum and has a thickness of 5 μm, and where the wire 16 is also made of aluminum and has a diameter comprised between 100 μm and 500 μm. In this connection, it should be noted how FIG. 1, as on the other hand also the subsequent figures, are not in scale.
Aluminum has a linear coefficient of thermal expansion (linear CTE) of approximately 25 ppm/° K, whereas silicon has a linear coefficient of thermal expansion of approximately 4 ppm/° K. This difference between the values of the coefficients of thermal expansion causes high mechanical stresses at the chip-to-wire interface, when the electronic power device 1 undergoes a succession of thermal cycles. In practice, from the standpoint of reliability, the interface between the wire 16 and the front metallization region 6 represents the weak point of the electronic power device 1, in which both shear stresses and flexural stresses are concentrated. These stresses may cause failure of the interface, in which case the front metallization region 6 and the wire 16 become electrically separate, with consequent impossibility of conveying current outside the electronic power device 1, through the wire 16.
In order to improve the reliability of the interface between the front metallization region 6 and the wire 16, there has been proposed the solution of making both the front metallization region 6 and the wire 16 of copper, as described, for example, in “Large Cu Wire Wedge Bonding Process for Power Devices”, by J. Ling et al., 13th Electronics Packaging Technology Conference, 2011.
Copper is harder than aluminum and has a linear coefficient of thermal expansion of approximately 17 ppm/° K. In addition, copper exhibits a greater current-carrying capacity as compared to aluminum and enables formation of interconnections of smaller size given the same current.
When the front metallization region 6 is made of copper, it may have a large thickness, in such a way as to limit substantially the possibility of the front metallization region 6 itself being subject to phenomena of damage such as cratering. On the other hand, the large thickness of the front metallization region 6 may entail, during the process of manufacture of the electronic power device 1, a warpage of the semiconductor wafer.